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NCP3063, NCP3063B, NCV3063 1.5 A, Step-Up/Down/ Inverting Switching Regulators
The NCP3063 Series is a higher frequency upgrade to the popular MC34063A and MC33063A monolithic DC-DC converters. These devices consist of an internal temperature compensated reference, comparator, a controlled duty cycle oscillator with an active current limit circuit, a driver and a high current output switch. This series was specifically designed to be incorporated in Step-Down, Step-Up and Voltage-Inverting applications with a minimum number of external components.
Features http://onsemi.com MARKING DIAGRAMS
8 1 SOIC-8 D SUFFIX CASE 751 1
3063x ALYW G
* * * * * * * *
Operation to 40 V Input Low Standby Current Output Switch Current to 1.5 A Output Voltage Adjustable Frequency Operation of 150 kHz Precision 1.5% Reference New Features: Internal Thermal Shutdown with Hysteresis New Features: Cycle-by-Cycle Current Limiting Pb-Free Packages are Available
V3063 ALYW G 1
NCP3063x AWL YYWWG 1 8 1 PDIP-8 P, P1 SUFFIX CASE 626 1 8 1 DFN-8 SUFFIX CASE 488 3063y ALYW G NCV3063 AWL YYWWG
Applications
* Step-Down, Step-Up and Inverting supply applications * High Power LED Lighting * Battery Chargers
8 NCP3063 SET dominant R Q 7 COMPARATOR - + Rs 0.15 W 6 R 0.2 V OSCILLATOR CT + - COMPARATOR 1.25 V REFERENCE REGULATOR CT 2.2 nF 4 3 D L 47 mH S 1 TSD
S Q
SET dominant
2
Vin
12 V + Cin 220 mF 5
Vout 3.3 V / 800 mA +
NCP3063x = Specific Device Code x=B A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G = Pb-Free Package (Note: Microdot may be in either location)
R1 2.4 kW
R2
3.9 kW
470 mF Cout
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet.
Figure 1. Typical Buck Application Circuit
(c) Semiconductor Components Industries, LLC, 2006
1
November, 2006 - Rev. 1
Publication Order Number: NCP3063/D
NCP3063, NCP3063B, NCV3063
PIN CONNECTIONS
Switch Collector Switch Emitter Timing Capacitor GND 2 3 4 (Top View) 1 8 7 6 5 N.C. Ipk Sense VCC Comparator Inverting Input
NCP3063 8 N.C. SET dominant R Q S 7 Ipk Sense COMPARATOR - + 0.2 V 6 +VCC COMPARATOR + - 1.25 V REFERENCE REGULATOR S Q R SET dominant OSCILLATOR CT 3 Timing Capacitor 2 Switch Emitter TSD 1 Switch Collector
5 Comparator Inverting Input
4 GND
Figure 2. Block Diagram
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NCP3063, NCP3063B, NCV3063
PIN DESCRIPTION
Pin No. 1 2 3 4 5 6 7 8 Pin Name Switch Collector Switch Emitter Timing Capacitor GND Comparator Inverting Input VCC Ipk Sense N.C. Internal Darlington switch collector Internal Darlington switch emitter Timing Capacitor to control the switching frequency Ground pin for all internal circuits Inverting input pin of internal comparator Voltage supply Peak Current Sense Input to monitor the voltage drop across an external resistor to limit the peak current through the circuit Pin not connected Description
MAXIMUM RATINGS (measured vs. pin 4, unless otherwise noted)
Rating VCC pin 6 Comparator Inverting Input pin 5 Darlington Switch Collector pin 1 Darlington Switch Emitter pin 2 (transistor OFF) Darlington Switch Collector to Emitter pin 1-2 Darlington Switch Current Ipk Sense pin 7 Power Dissipation and Thermal Characteristics PDIP-8 Thermal Resistance Junction-to-Air SOIC-8 Thermal Resistance Junction-to-Air Storage Temperature Range Maximum Junction Temperature Operating Junction Temperature Range (Note 3) NCP3063 NCP3063B, NCV3063 C/W RqJA RqJA TSTG TJ MAX TJ 0 to +70 -40 to +125 100 C/W 180 -65 to +150 +150 C C C Symbol VCC VCII VSWC VSWE VSWCE ISW VIPK Value 0 to +40 - 0.2 to + VCC 0 to +40 - 0.6 to + VCC 0 to +40 1.5 - 0.2 to VCC + 0.2 Unit V V V V V A V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device series contains ESD protection and exceeds the following tests: Pin 1-8: Human Body Model 2000 V per AEC Q100-002; 003 or JESD22/A114; A115 Machine Model Method 200 V 2. This device contains latch-up protection and exceeds 100 mA per JEDEC Standard JESD78. 3. The relation between junction temperature, ambient temperature and Total Power dissipated in IC is TJ = TA + Rq * PD 4. The pins which are not defined may not be loaded by external signals
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NCP3063, NCP3063B, NCV3063
ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, TJ = Tlow to Thigh [Note 5], unless otherwise specified)
Symbol OSCILLATOR fOSC IDISCHG / ICHG VIPK(Sense) Frequency Discharge to Charge Current Ratio Current Limit Sense Voltage (VPin 5 = 0 V, CT = 2.2 nF, TJ = 25C) (Pin 7 to VCC, TJ = 25C) (TJ = 25C) (Note 6) 110 5.5 165 150 6.0 200 190 6.5 235 kHz - mV Characteristic Conditions Min Typ Max Unit
OUTPUT SWITCH (Note 7) VSWCE(DROP) Darlington Switch Collector to Emitter Voltage Drop IC(OFF) Collector Off-State Current (ISW = 1.0 A, Pin 2 to GND, TJ = 25C) (Note 7) (VCE = 40 V) 1.0 0.01 1.3 100 V mA
COMPARATOR VTH Threshold Voltage TJ = 25C NCP3063 NCP3063B, NCV3063 REGLiNE ICII in Threshold Voltage Line Regulation Input Bias Current (VCC = 5.0 V to 40 V) (Vin = Vth) -1.5 -2 -6.0 -1000 2.0 -100 1.250 +1.5 +2 6.0 1000 V % % mV nA
TOTAL DEVICE ICC Supply Current (VCC = 5.0 V to 40 V, CT = 2.2 nF, Pin 7 = VCC, VPin 5 > Vth, Pin 2 = GND, remaining pins open) 160 10 7.0 mA
Thermal Shutdown Threshold Hysteresis
C C
5. NCP3063: Tlow = 0C, Thigh = +70C; NCP3063B, NCV3063: Tlow = -40C, Thigh = +125C 6. The VIPK(Sense) Current Limit Sense Voltage is specified at static conditions. In dynamic operation the sensed current turn-off value depends on comparator response time and di/dt current slope. See the Operating Description section for details. 7. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient temperature as possible. 8. NCV prefix is for automotive and other applications requiring site and change control.
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NCP3063, NCP3063B, NCV3063
200 180 160 FREQUENCY (kHz) 140 120 100 80 60 40 20 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Ct, CAPACITANCE (nF) FREQUENCY (Hz) 170 160 150 140 130 120 110 3 7 12 16 21 25 29 34 38 40 190 180 CT = 2.2 nF TJ = 25C
VCC, SUPPLY VOLTAGE (V)
Figure 3. Oscillator Frequency vs. Oscillator Timing Capacitor
Figure 4. Oscillator Frequency vs. Supply Voltage
2.4 2.2 VOLTAGE DROP (V) 2.0 1.8 1.6 1.4 1.2 1.0 -50 0 50 100 150 VCC = 5.0 V IE = 1 A VOLTAGE DROP (V)
1.25 VCC = 5.0 V IC = 1 A
1.20
1.15
1.10
1.05 1.0 -50
0
50
100
150
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 5. Emitter Follower Configuration Output Darlington Switch Voltage Drop vs. Temperature
Figure 6. Common Emitter Configuration Output Darlington Switch Voltage Drop vs. Temperature
2.0 1.9 1.8 VOLTAGE DROP (V) 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0 0.5 1.0 1.5 IE, EMITTER CURRENT (A) VCC = 5.0 V TJ = 25C VOLTAGE DROP (V)
1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0 0.5 1.0 1.5 IC, COLLECTOR CURRENT (A) VCC = 5.0 V TJ = 25C
Figure 7. Emitter Follower Configuration Output Darlington Switch Voltage Drop vs. Emitter Current
Figure 8. Common Emitter Configuration Output Darlington Switch Voltage Drop vs. Collector Current
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NCP3063, NCP3063B, NCV3063
Vth, COMPARATOR THRESHOLD VOLTAGE (V) 1.30 Vipk(sense), CURRENT LIMIT SENSE VOLTAGE (V) 5 20 35 50 65 80 95 110 125 0.30 0.28 0.26 0.24 0.22 0.20 0.18 0.16 0.14 0.12 0.10 -40 -25 -10
1.28
1.26
1.24
1.22 1.20 -40 -25 -10
5
20
35
50
65
80
95
110 125
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 9. Comparator Threshold Voltage vs. Temperature
6.0 ICC, SUPPLY CURRENT (mA) 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 3.0 8.0 13 18 23 28
Figure 10. Current Limit Sense Voltage vs. Temperature
CT = 2.2 nF Pin 5, 7 = VCC Pin 2 = GND 33 38 43
VCC, SUPPLY VOLTAGE (V)
Figure 11. Standby Supply Current vs. Supply Voltage
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NCP3063, NCP3063B, NCV3063
INTRODUCTION The NCP3063 is a monolithic power switching regulator optimized for dc to dc converter applications. The combination of its features enables the system designer to directly implement step-up, step-down, and voltage- inverting converters with a minimum number of external components. Potential applications include cost sensitive consumer products as well as equipment for industrial markets. A representative block diagram is shown in Figure 2. Operating Description The NCP3063 is a hysteric, dc-dc converter that uses a gated oscillator to regulate output voltage. In general, this mode of operation is somewhat analogous to a capacitor charge pump and does not require dominant pole loop compensation for converter stability. The Typical Operating Waveforms are shown in Figure 12. The output voltage waveform shown is for a step-down converter with the ripple and phasing exaggerated for clarity. During initial converter startup, the feedback comparator senses that the output voltage level is below nominal. This causes the output switch to turn on and off at a frequency and duty cycle controlled by the oscillator, thus pumping up the output filter capacitor. When the output voltage level reaches nominal, the output switch next cycle turning on is inhibited. The feedback comparator will enable the switching immediately when the load current causes the output voltage to fall below nominal. Under these conditions, output switch conduction can be enabled for a partial oscillator cycle, a partial cycle plus a complete cycle, multiple cycles, or a partial cycle plus multiple cycles. (See AN920/D for more information). Oscillator The oscillator frequency and off-time of the output switch are programmed by the value selected for timing capacitor CT. Capacitor CT is charged and discharged by a 1 to 6 ratio internal current source and sink, generating a positive going sawtooth waveform at Pin 3. The oscillator peak and valley voltage difference is 500 mV typically. To calculate the CT capacitor value for required oscillator frequency, use the equations found in Figure 13. An Excel based design tool can be found at www.onsemi.com on the NCP3063 product page.
1 Feedback Comparator Output 0 1 IPK Comparator Output 0
Timing Capacitor, CT
On Output Switch Off
Nominal Output Voltage Level
Output Voltage Startup Operation
Figure 12. Typical Operating Waveforms
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NCP3063, NCP3063B, NCV3063
Peak Current Sense Comparator
With a voltage ripple gated converter operating under normal conditions, output switch conduction is initiated by the Voltage Feedback comparator and terminated by the oscillator. Abnormal operating conditions occur when the converter output is overloaded or when feedback voltage sensing is lost. Under these conditions, the Ipk Current Sense comparator will protect the Darlington output Switch. The switch current is converted to a voltage by inserting a fractional ohm resistor, RSC, in series with VCC and the Darlington output switch. The voltage drop across RSC is monitored by the Current Sense comparator. If the voltage drop exceeds 200 mV with respect to VCC, the comparator will set the latch and terminate output switch conduction on a cycle-by-cycle basis. This Comparator/Latch configuration ensures that the Output Switch has only a single on-time during a given oscillator cycle.
Real Vturn-off on Rs Resistor di/dt slope Vipk(sense) Io t_delay I1 I through the Darlington Switch
Real Vturn-off on Rsc resistor
Vturn_off + Vipk(sense) ) Rs @ (t_delay @ di dt)
Typical Ipk comparator response time t_delay is 350 ns. The di/dt current slope is growing with voltage difference on the inductor pins and with decreasing inductor value. It is recommended to check the real max peak current in the application at worst conditions to be sure that the max peak current will never get over the 1.5 A Darlington Switch Current max rating.
Thermal Shutdown
Internal thermal shutdown circuitry is provided to protect the IC in the event that the maximum junction temperature is exceeded. When activated, typically at 160C, the Output Switch is disabled. The temperature sensing circuit is designed with 10C hysteresis. The Switch is enabled again when the chip temperature decreases to at least 150C threshold. This feature is provided to prevent catastrophic failures from accidental device overheating. It is not intended to be used as a replacement for proper heatsinking.
Output Switch
The VIPK(Sense) Current Limit Sense Voltage threshold is specified at static conditions. In dynamic operation the sensed current turn-off value depends on comparator response time and di/dt current slope.
The output switch is designed in a Darlington configuration. This allows the application designer to operate at all conditions at high switching speed and low voltage drop. The Darlington Output Switch is designed to switch a maximum of 40 V collector to emitter voltage and current up to 1.5 A.
APPLICATIONS Figures 14 through 22 show the simplicity and flexibility of the NCP3063. Three main converter topologies are demonstrated with actual test data shown below each of the circuit diagrams. Figure 13 gives the relevant design equations for the key parameters. Additionally, a complete application design aid for the NCP3063 can be found at www.onsemi.com.
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NCP3063, NCP3063B, NCV3063
(See Notes 9, 10, 11) Step-Down Step-Up Voltage-Inverting
ton toff ton
Vout ) VF Vin * VSWCE * Vout
ton toff
Vout ) VF * Vin Vin * VSWCE
ton toff
|Vout| ) VF Vin * VSWCE
ton toff
f CT IL(avg) Ipk (Switch) RSC L Vripple(pp) DIL Vout
ton toff
)1
f
ton toff
)1 * 343 @ 10 *12
f
ton toff
)1
CT + 381.6 @ 10 fosc Iout IL(avg) ) DIL 2 Iout
*6
ton )1 toff DIL 2
Iout
ton )1 toff DIL 2
IL(avg) )
IL(avg) )
0.20 Ipk (Switch) Vin * VSWCE * Vout ton DIL 1 8 f CO
2
0.20 Ipk (Switch) Vin * VSWCE ton DIL tI [ on out ) DIL @ ESR CO R VTH 2 ) 1 R1
0.20 Ipk (Switch) Vin * VSWCE ton DIL tI [ on out ) DIL @ ESR CO R VTH 2 ) 1 R1
) (ESR) 2
R VTH 2 ) 1 R1
The Following Converter Characteristics Must Be Chosen:
Vin - Nominal operating input voltage. Vout - Desired output voltage. Iout - Desired output current. DIL - Desired peak-to-peak inductor ripple current. For maximum output current it is suggested that DIL be chosen to be less than 10% of the average inductor current IL(avg). This will help prevent Ipk (Switch) from reaching the current limit threshold set by RSC. If the design goal is to use a minimum inductance value, let DIL = 2(IL(avg)). This will proportionally reduce converter output current capability. f - Maximum output switch frequency. Vripple(pp) - Desired peak-to-peak output ripple voltage. For best performance the ripple voltage should be kept to a low value since it will directly affect line and load regulation. Capacitor CO should be a low equivalent series resistance (ESR) electrolytic designed for switching regulator applications.
9. VSWCE - Darlington Switch Collector to Emitter Voltage Drop, refer to Figures 5, 6, 7 and 8. 10. VF - Output rectifier forward voltage drop. Typical value for 1N5819 Schottky barrier rectifier is 0.4 V. 11. The calculated ton/toff must not exceed the minimum guaranteed oscillator charge to discharge ratio.
Figure 13. Design Equations
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NCP3063, NCP3063B, NCV3063
R201 0R15 +VIN = +12 V 1 J201 C201 0.1 mF J202 1 GND + C202 220 mF / 50 V
8 7 6 5
U201 N.C. SWC SWE IPK TCAP VCC COMP GND NCP3063
1 2 3 4
L201 D201
47 mH C206 0.1 mF
+VOUT = +3.3 V / 800 mA 1 J203 + C205 470 mF / 25 V J204 1 GND
C203 2.2 nF
1N5819
R203 R202 2K4 1% 3K9 1%
Figure 14. Typical Buck Application Schematic Value of Components
Name L201 D201 C202 C205 C203 Value 47 mH, Isat > 1.5 A 1 A, 40 V Schottky Rectifier 220 mF, 50 V, Low ESR 470 mF, 25 V, Low ESR 2.2 nF Ceramic Capacitor Name R201 R202 R203 C201 C202 Value 150 mW, 0.5 W 2.40 kW 3.90 kW 100 nF Ceramic Capacitor 100 nF Ceramic Capacitor
Test Results
Test Line Regulation Load Regulation Output Ripple Efficiency Short Circuit Current Condition Vin = 9 V to 12 V, Io = 800 mA Vin = 12 V, Io = 80 mA to 800 mA Vin = 12 V, Io = 40 mA to 800 mA Vin = 12 V, Io = 400 mA to 800 mA Vin = 12 V, Rload = 0.15 W 8 mV 9 mV 85 mVpp > 73% 1.25 A Results
76 74 EFFICIENCY (%) 72 70 68 66 64 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 OUTPUT LOAD (Adc)
Figure 15. Buck Demoboard Layout
Figure 16. Efficiency vs. Output Current for the Buck Demo Board at Vin = 12 V, Vout = 3.3 V, TA = 255C
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NCP3063, NCP3063B, NCV3063
L101 R101 0R15 +VIN = +12 V 1 J101 C101 0.1 mF J102 1 GND R102 1K0 1% 18K0 1% + C102 470 mF / 25 V 8 7 6 5 100 mH U101 N.C. SWC 1 SWE 2 IPK 3 VCC TCAP COMP GND 4 NCP3063
D101
1N5819 +
+VOUT = +24 V / 350 mA 1 J103
C106 C103 2.2 nF 0.1 mF
C105 330 mF / 50 V J104 1 GND
R103
Figure 17. Typical Boost Application Schematic
Value of Components
Name L101 D101 C102 C105 C103 Value 100 mH, Isat > 1.5 A 1 A, 40 V Schottky Rectifier 470 mF, 25 V, Low ESR 330 mF, 50 V, Low ESR 2.2 nF Ceramic Capacitor Name R101 R102 R103 C101 C106 Value 150 mW, 0.5 W 1.00 kW 18.00 kW 100 nF Ceramic Capacitor 100 nF Ceramic Capacitor
Test Results
Test Line Regulation Load Regulation Output Ripple Efficiency Condition Vin = 9 V to 15 V, Io = 250 mA Vin = 12 V, Io = 30 mA to 350 mA Vin = 12 V, Io = 10 mA to 350 mA Vin = 12 V, Io = 50 mA to 350 mA 2 mV 5 mV 350 mVpp > 85.5% Results
90 89 88 EFFICIENCY (%) 87 86 85 84 83 82 81 80 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 OUTPUT LOAD (Adc)
Figure 18. Boost Demoboard Layout
Figure 19. Efficiency vs. Output Current for the Boost Demo Board at Vin = 12 V, Vout = 24 V, TA = 255C
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NCP3063, NCP3063B, NCV3063
R501 0R15 +VIN = +5 V 1 J501 C501 0.1 mF J502 1 GND + C502 330 mF / 25 V
8 7 6 5
U501 N.C. SWC SWE IPK TCAP VCC COMP GND NCP3063
1 2 3 4
C503 2.2 nF
L501 22 mH D501 1N5819 VOUT = -12 V / 100 mA 1 J503 C506 0.1 mF C505 + 470 mF / 35 V
R503 R502 16K9 1% 1K96 1%
1 J504 GND
Figure 20. Typical Voltage Inverting Application Schematic
Value of Components
Name L501 D501 C502 C505 C503 Value 22 mH, Isat > 1.5 A 1 A, 40 V Schottky Rectifier 330 mF, 25 V, Low ESR 470 mF, 35 V, Low ESR 2.2 nF Ceramic Capacitor Name R501 R502 R503 C501 C506 Value 150 mW, 0.5 W 16.9 kW 1.96 kW 100 nF Ceramic Capacitor 100 nF Ceramic Capacitor
Test Results
Test Line Regulation Load Regulation Output Ripple Efficiency Short Circuit Current Condition Vin = 4.5 V to 6 V, Io = 50 mA Vin = 5 V, Io = 10 mA to 100 mA Vin = 5 V, Io = 0 mA to 100 mA Vin = 5 V, Io = 100 mA Vin = 5 V, Rload = 0.15 W 1.5 mV 1.6 mV 300 mVpp 49.8% 0.885 A Results
52 50 EFFICIENCY (%) 48 46 44 42 40 38 36 0 20 40 60 80 100 OUTPUT LOAD (mAdc)
Figure 21. Voltage Inverting Demoboard Layout
Figure 22. Efficiency vs. Output Current for the Voltage Inverting Demo Board at Vin = +5 V, Vout = -12 V, TA = 255C
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NCP3063, NCP3063B, NCV3063
ORDERING INFORMATION
Device NCP3063PG NCP3063BPG NCP3063DR2G NCP3063BDR2G NCP3063 NCV3063PG NCV3063DR2G Package PDIP-8 (Pb-Free) PDIP-8 (Pb-Free) SOIC-8 (Pb-Free) SOIC-8 (Pb-Free) DFN-8 (Pb-Free) PDIP-8 (Pb-Free) SOIC-8 (Pb-Free) Shipping 50 Units / Rail 50 Units / Rail 2500 Units / Tape & Reel 2500 Units / Tape & Reel TBD 50 Units / Rail 2500 Units / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. NCV prefix is for automotive and other applications requiring site and change control.
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NCP3063, NCP3063B, NCV3063
PACKAGE DIMENSIONS
SOIC-8 NB CASE 751-07 ISSUE AH
-X- A
8 5
B
1 4
S
0.25 (0.010)
M
Y
M
-Y- G C -Z- H D 0.25 (0.010)
M SEATING PLANE
K
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
DIM A B C D G H J K M N S
SOLDERING FOOTPRINT*
1.52 0.060
7.0 0.275
4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NCP3063, NCP3063B, NCV3063
PACKAGE DIMENSIONS
8 LEAD PDIP CASE 626-05 ISSUE L
8 5
-B-
1 4
NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC --- 10_ 0.76 1.01 AC IN DC + IN DC - IN AC IN GROUND OUTPUT AUXILIARY VCC INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC --- 10_ 0.030 0.040
F
NOTE 2
-A- L
C -T-
SEATING PLANE
J N D K
M
M TA
M
H
G 0.13 (0.005) B
M
STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8.
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NCP3063, NCP3063B, NCV3063
PACKAGE DIMENSIONS
8 PIN DFN, 4x4 CASE 488AF-01 ISSUE B
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.25 0.35 4.00 BSC 1.91 2.21 4.00 BSC 2.09 2.39 0.80 BSC 0.20 --- 0.30 0.50
D
PIN ONE IDENTIFICATION
A
8X
L
1
B
8X
K
E
2X
0.15 C b
2X 8X NOTE 3
0.15 C
TOP VIEW
0.10 C A B 0.05 C
0.10 C A
8X
0.08 C
SEATING PLANE
A1
(A3)
SIDE VIEW
C
SOLDERING FOOTPRINT*
4.30 2.21
8X
8X
0.35
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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PUBLICATION ORDERING INFORMATION
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CC CC CC CC CC CC
CC CC CC CC CC CC
1
C CC C CC C CC C CC C CC
8 5
D2
4
E2
e
BOTTOM VIEW
DIM A A1 A3 b D D2 E E2 e K L
CCC CC
2.39
0.63
0.40 0.80 PITCH
2.75
NCP3063/D

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